Udi Finkelstein 6378e2cd46 First draft of Verilog parser support for specify blocks and parameters. ...

The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST

2018-03-27 14:34:00 +02:00

..

ast

Add $allconst and $allseq cell types

2018-02-23 13:14:47 +01:00

blif

Increase maximum LUT size in blifparse to 12 bits

2017-09-27 15:27:42 +02:00

ilang

Added avail params to ilang format, check module params in 'hierarchy -check'

2016-10-22 11:05:49 +02:00

json

Parse reals as string in JSON front-end

2017-09-26 14:37:03 +02:00

liberty

Improve handling of "bus" pins in liberty front-end (some files use bus.pin.direction)

2018-02-15 17:36:08 +01:00

verific

Fix handling of unclocked immediate assertions in Verific front-end

2018-03-26 13:04:10 +02:00

verilog

First draft of Verilog parser support for specify blocks and parameters.

2018-03-27 14:34:00 +02:00