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YosysHQ.yosys/passes/cmds
Marcelina Kościelnicka 0aad88a2fb Add clean_zerowidth pass, use it for Verilog output.
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
2021-12-12 19:56:50 +01:00
..
2021-11-12 15:09:58 +01:00
2021-08-11 13:34:10 +02:00