Clifford Wolf 679bc6507f

Merge pull request #1252 from YosysHQ/clifford/fix1231 ...

Fix handling of functions/tasks without top-level begin-end block

2019-08-07 12:14:54 +02:00

..

aiger

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

ast

Fix handling of functions/tasks without top-level begin-end block, fixes #1231

2019-08-06 18:06:14 +02:00

blif

Add missing "[options]" to read_blif help

2019-02-08 12:41:39 -08:00

ilang

Allow attributes on individual switch cases in RTLIL.

2019-07-08 11:34:58 +00:00

json

Update JSON front-end to process new attr/param encoding

2019-08-01 12:48:22 +02:00

liberty

Fix typo, double "of"

2019-07-16 11:03:30 +02:00

verific

Call "read_verilog" with -defer from "read"

2019-07-29 10:29:36 +02:00

verilog

verilog_lexer: Increase YY_BUF_SIZE to 65536

2019-07-26 13:35:39 +01:00