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YosysHQ.yosys/passes
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Clifford Wolf e9a756aa7a Merge pull request #1213 from YosysHQ/eddie/wreduce_add 
wreduce/opt_expr: improve width reduction for $add and $sub cells
2019-08-07 14:27:35 +02:00
..
cmds
Tweak default gate costs, cleanup "stat -tech cmos"
2019-08-07 10:25:51 +02:00
equiv
Add -undef option to equiv_opt, passed to equiv_induct
2019-04-26 11:16:48 -07:00
fsm
fsm_opt: Fix runtime error for FSMs without a reset state
2019-02-07 10:35:36 +00:00
hierarchy
Use input default values in hierarchy pass
2019-06-19 11:49:20 +02:00
memory
Error out if enable > dbits
2019-07-13 03:39:23 -07:00
opt
Move LSB-trimming functionality from wreduce to opt_expr
2019-08-06 15:25:50 -07:00
pmgen
From master
2019-05-28 09:37:50 -07:00
proc
proc_prune: Promote partially redundant assignments.
2019-08-01 13:09:55 +02:00
sat
Fix tests/various/async FFL test
2019-07-09 22:44:39 +02:00
techmap
Redesign of cell cost API
2019-08-07 01:12:14 +02:00
tests
flowmap: implement depth relaxation.
2019-01-08 01:13:05 +00:00