1
0
mirror of synced 2026-05-03 06:40:15 +00:00
Files
YosysHQ.yosys/tests/ecp5/add_sub.v
2019-09-03 11:53:37 +03:00

14 lines
133 B
Verilog

module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x + y;
assign B = x - y;
endmodule