github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-25 11:56:22 +00:00
Code Issues Releases Wiki Activity
Files
5f76729cbbcc6fd98f1cacbcf4e598cd74f30857
YosysHQ.yosys/techlibs/intel/max10
History
Richard Herveille 2893938355 Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
..
cells_arith.v
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cells_map.v
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cells_sim.v
Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
dsp_map.v
dsp_map for MAX10
2024-03-06 02:43:30 +01:00