12 lines
188 B
Verilog
12 lines
188 B
Verilog
module t_gate_switch (L,R,nC,C);
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inout L;
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inout R;
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input nC;
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input C;
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//Syntax: keyword unique_name (drain. source, gate);
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pmos p1 (L,R,nC);
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nmos p2 (L,R,C);
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endmodule
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