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60eaaf6e0f7bf1020ee62f8b77e8ead5dcbb8f99
YosysHQ.yosys
/
frontends
/
verilog
History
Clifford Wolf
ec4565009a
Add "read_verilog -pwires" feature,
closes
#1106
...
Signed-off-by: Clifford Wolf <
clifford@clifford.at
>
2019-06-19 14:38:50 +02:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Added support for unsized constants,
fixes
#1022
2019-05-27 11:42:10 +02:00
Makefile.inc
Read bigger Verilog files.
2019-05-18 14:20:30 +03:00
preproc.cc
Support SystemVerilog `` extension for macros
2018-05-17 00:09:56 -04:00
verilog_frontend.cc
Add "read_verilog -pwires" feature,
closes
#1106
2019-06-19 14:38:50 +02:00
verilog_frontend.h
Add specify parser
2019-04-23 21:36:59 +02:00
verilog_lexer.l
Fixed brojen $error()/$info/$warning() on non-generate blocks
2019-06-11 02:52:06 +03:00
verilog_parser.y
Add "read_verilog -pwires" feature,
closes
#1106
2019-06-19 14:38:50 +02:00
