Robert O'Callahan 09b493cfcd Update techlibs to avoid bits()

2025-09-16 03:17:23 +00:00

..

common

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

pp3

synth_quicklogic: rearrange files to prepare for adding more architectures

2023-12-04 15:52:02 +01:00

qlf_k6n10f

Drop timestamp in generate_bram_types_sim.py

2024-10-30 08:47:18 +01:00

.gitignore

add dsp inference

2023-12-04 15:52:02 +01:00

Makefile.inc

add ioff inference for qlf_k6n10f

2025-01-24 21:17:15 +01:00

ql_bram_merge.cc

Fix Windows build by forcing initialization order, fixes #4068

2024-01-02 11:26:48 +01:00

ql_bram_types.cc

add dsp inference

2023-12-04 15:52:02 +01:00

ql_dsp_io_regs.cc

Fix Windows build by forcing initialization order, fixes #4068

2024-01-02 11:26:48 +01:00

ql_dsp_macc.cc

Fix out of tree build

2023-12-06 09:11:51 +01:00

ql_dsp_macc.pmg

ql_dsp_macc: Tune DSP inference code

2023-12-04 15:52:02 +01:00

ql_dsp_simd.cc

Update techlibs to avoid bits()

2025-09-16 03:17:23 +00:00

ql_ioff.cc

create duplicate IOFFs if multiple output ports are connected to the same register

2025-01-31 11:28:57 +01:00

synth_quicklogic.cc

Remove .c_str() from stringf parameters

2025-09-01 23:34:42 +00:00