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6282c1f27d28a4ba700dfd0db22d5745b094e2ad
YosysHQ.yosys
/
backends
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edif
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Clifford Wolf
cff3195caa
Improve EDIF lib_cell_ports scan
2023-06-20 10:42:05 +02:00
..
edif.cc
Improve EDIF lib_cell_ports scan
2023-06-20 10:42:05 +02:00
Makefile.inc
Added edif backend (still under construction)
2013-08-22 11:34:55 +02:00
runtest.py
Add generation of logic cells to EDIF back-end runtest.py
2017-03-19 14:57:40 +01:00
