11 lines
146 B
Verilog
11 lines
146 B
Verilog
module test (in1, in2, out);
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input in1, in2;
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output reg out;
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always @ ( in1 or in2)
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if(in1 > in2)
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out = in1;
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else
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out = in2;
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endmodule
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