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YosysHQ.yosys/tests/hana/test_simulation_techmap_and_19_tech.v
Clifford Wolf 7764d0ba1d initial import
2013-01-05 11:13:26 +01:00

8 lines
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Verilog

module TECH_AND18(input [17:0] in, output out);
assign out = ∈
endmodule
module TECH_AND4(input [3:0] in, output out);
assign out = ∈
endmodule