7 lines
192 B
Verilog
7 lines
192 B
Verilog
module TECH_XOR5(input [4:0] in, output out);
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assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
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endmodule
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module TECH_XOR2(input [1:0] in, output out);
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assign out = in[0] ^ in[1];
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endmodule
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