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64925b4e8f7890f5447d9655b2c69dd59a93f7cd
YosysHQ.yosys
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backends
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verilog
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Clifford Wolf
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
...
Signed-off-by: Clifford Wolf <
clifford@clifford.at
>
2019-04-23 21:36:59 +02:00
..
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
verilog_backend.cc
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
2019-04-23 21:36:59 +02:00