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64925b4e8f7890f5447d9655b2c69dd59a93f7cd
YosysHQ.yosys/frontends/verilog
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Clifford Wolf 64925b4e8f Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:57:10 +02:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Convert more log_error() to log_file_error() where possible.
2018-07-20 09:37:44 -07:00
Makefile.inc
Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
2019-03-29 16:32:44 +01:00
preproc.cc
Support SystemVerilog `` extension for macros
2018-05-17 00:09:56 -04:00
verilog_frontend.cc
Add specify parser
2019-04-23 21:36:59 +02:00
verilog_frontend.h
Add specify parser
2019-04-23 21:36:59 +02:00
verilog_lexer.l
Improve $specrule interface
2019-04-23 22:57:10 +02:00
verilog_parser.y
Improve $specrule interface
2019-04-23 22:57:10 +02:00