Robert O'Callahan 8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.

2025-07-22 10:38:38 +00:00

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.gitignore

Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.

2025-07-22 10:38:38 +00:00

add_sub.ys

ice40, ecp5, gowin: enable ABC9 by default

2023-11-13 15:28:13 +00:00

adffs.ys

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bug1597.ys

Reenable existing equiv_opt tests

2022-10-07 16:04:51 +02:00

bug1598.ys

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bug1626.ys

Remove references to ilang

2024-11-05 12:36:31 +13:00

bug1644.il.gz

Add #1644 testcase

2020-01-17 15:57:52 -08:00

bug1644.ys

Remove references to ilang

2024-11-05 12:36:31 +13:00

bug2061.ys

opt_lut: Allow more than one -dlogic per cell type.

2021-07-29 17:30:07 +02:00

counter.ys

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dffs.ys

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dpram.v

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dpram.ys

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fsm.ys

synth_ice40: Use opt_dff.

2020-07-30 22:26:20 +02:00

ice40_dsp_const.ys

ice40_dsp: add test

2025-04-09 21:21:46 +03:00

ice40_dsp.ys

test: ice40_dsp test to read +/ice40/cells_sim.v for default params

2020-04-22 16:35:35 -07:00

ice40_opt.ys

Fix tests for check in equiv_opt

2022-10-07 16:04:51 +02:00

ice40_wrapcarry.ys

Change attribute search value to specify precise location instead of simple line number.

2020-02-24 02:41:08 +00:00

latches.ys

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logic.ys

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macc.v

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macc.ys

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memories.ys

ice40: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

mul.ys

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mux.ys

ice40, ecp5, gowin: enable ABC9 by default

2023-11-13 15:28:13 +00:00

rom.v

Revert insertion of 'reg', leave note behind

2020-01-01 09:05:46 -08:00

rom.ys

Update tests

2023-06-09 14:41:45 +02:00

run-test.sh

test: restore verific handling, nicer naming

2024-12-13 10:24:47 +01:00

shifter.ys

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spram.v

Tests for ram_style = "huge"

2023-02-21 05:23:15 +13:00

spram.ys

Tests for ram_style = "huge"

2023-02-21 05:23:15 +13:00

tribuf.ys

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