This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-04-13 09:02:00 +00:00
Code
Issues
Releases
Wiki
Activity
Files
65234d4b24edd1ec8ec5d41df2d56d76fa41dcc5
YosysHQ.yosys
/
techlibs
/
ice40
History
David Shah
cd65eeb3b3
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
...
Signed-off-by: David Shah <
davey1576@gmail.com
>
2018-07-13 13:09:18 +02:00
..
tests
…
.gitignore
…
arith_map.v
…
brams_init.py
…
brams_map.v
…
brams.txt
…
cells_map.v
Improving vpr output support.
2018-04-18 16:55:12 -07:00
cells_sim.v
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
2018-07-13 13:09:18 +02:00
ice40_ffinit.cc
Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations
2016-07-08 14:41:36 +02:00
ice40_ffssr.cc
Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations
2016-07-08 14:41:36 +02:00
ice40_opt.cc
Fix ice40_opt for cases where a port is connected to a signal with width != 1
2018-06-11 18:12:42 +02:00
latches_map.v
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
Makefile.inc
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
synth_ice40.cc
Add "synth_ice40 -json"
2018-06-13 13:35:10 +02:00
