github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-24 03:27:10 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/passes
History
Eddie Hung 29d446d758 Cleanup
2019-09-19 10:39:00 -07:00
..
cmds
Revert "SigSet<Cell*> to use stable compare class"
2019-09-13 09:49:15 -07:00
equiv
Add equiv_opt -multiclock
2019-09-11 13:55:59 +01:00
fsm
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
hierarchy
Adopt @cliffordwolf's suggestion
2019-09-03 12:18:50 -07:00
memory
stoi -> atoi
2019-08-07 11:09:17 -07:00
opt
Revert "SigSet<Cell*> to use stable compare class"
2019-09-13 09:49:15 -07:00
pmgen
Cleanup
2019-09-19 10:39:00 -07:00
proc
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
sat
Revert "SigSet<Cell*> to use stable compare class"
2019-09-13 09:49:15 -07:00
techmap
Explicitly order function arguments
2019-09-13 16:18:05 -07:00
tests
Document (* gentb_skip *) attr for test_autotb
2019-09-06 13:28:15 -07:00