Dan Ravensloft 67b4ce06e0 intel: Map M9K BRAM only on families that have it ...

This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.

2019-07-23 18:11:11 +01:00

..

a10gx

Clean whitespace and permissions in techlibs/intel

2017-10-05 16:23:49 +02:00

common

intel: Map M9K BRAM only on families that have it

2019-07-23 18:11:11 +01:00

cyclone10

Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

2018-03-31 22:48:47 -06:00

cycloneiv

Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

2018-03-31 22:48:47 -06:00

cycloneive

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

cyclonev

Fixing issues in CycloneV cell sim

2019-04-11 19:59:03 -05:00

max10

Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

2018-03-31 22:48:47 -06:00

Makefile.inc

intel: Map M9K BRAM only on families that have it

2019-07-23 18:11:11 +01:00

synth_intel.cc

intel: Map M9K BRAM only on families that have it

2019-07-23 18:11:11 +01:00