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YosysHQ.yosys/tests
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Jannis Harder 5abaa59080
Merge pull request #3537 from jix/xprop 
New xprop pass
2023-01-11 16:26:04 +01:00
..
aiger
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
arch
fabulous: Allow adding extra custom prims and map rules
2022-11-17 13:34:58 +01:00
asicworld
Fix FIRRTL to Verilog process instance subfield assignment.
2019-02-25 16:18:13 -08:00
bind
Add support for parsing the SystemVerilog 'bind' construct
2021-07-16 09:31:39 -04:00
blif
Adding check for BLIF names command input plane size.
2022-08-21 23:18:20 -05:00
bram
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
errors
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
fsm
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
hana
…
liberty
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
lut
Forgot to commit
2019-07-16 12:44:26 -07:00
memfile
Added 'set -e' into tests/memfile/run-test.sh
2020-02-06 10:45:40 -03:00
memlib
Add memory_libmap tests.
2022-05-18 17:32:56 +02:00
memories
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
opt
simplemap: Map $xnor to $_XNOR_ cells
2022-11-29 19:06:45 +01:00
opt_share
tests: Parallelize
2020-09-21 15:07:02 +02:00
proc
proc_rom: Add special handling of const-0 address bits.
2022-05-18 17:32:30 +02:00
realmath
…
rpc
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
sat
Proper example code
2022-03-14 15:39:11 +01:00
select
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 15:35:05 -07:00
share
…
sim
Replace GNU specific invocation of basename(1) with the equivalent
2022-10-23 11:02:18 +13:00
simple
verilog: Support module-scoped task/function calls
2022-10-29 15:14:11 -04:00
simple_abc9
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
smv
…
sva
verific: Use new value change logic also for $stable of wide signals.
2022-05-11 13:05:27 +02:00
svinterfaces
Add a test for interfaces on modules loaded on-demand
2021-07-14 22:54:50 -04:00
svtypes
Support for packed multidimensional arrays within packed structs
2022-12-03 19:54:47 +01:00
techmap
Reenable existing equiv_opt tests
2022-10-07 16:04:51 +02:00
tools
support file locations containing spaces
2022-08-08 20:30:50 +02:00
unit
Build hotfix in tests/unit/Makefile
2016-12-11 10:58:49 +01:00
various
simplify: regression test for AST_CELLARRAY simplification issue
2022-12-07 18:41:55 +01:00
verilog
verilog: fix width/sign detection for functions
2022-05-30 16:45:39 -04:00
vloghtb
Use HTTPS for website links, gatecat email
2021-06-09 12:16:56 +02:00
xprop
New xprop pass to encode 3-valued x-propagation using 2-valued logic
2022-11-30 19:01:28 +01:00
gen-tests-makefile.sh
support file locations containing spaces
2022-08-08 20:30:50 +02:00