Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates

2017-05-17 09:08:29 +02:00

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altera_intel

Squelch trailing whitespace

2017-04-12 15:11:09 +02:00

common

Add $_ANDNOT_ and $_ORNOT_ gates

2017-05-17 09:08:29 +02:00

gowin

Indenting fixes in gowin sim cell lib

2016-11-08 18:54:00 +01:00

greenpak4

Squelch trailing whitespace

2017-04-12 15:11:09 +02:00

ice40

iCE40 flow is not experimental anymore

2016-11-01 11:32:02 +01:00

xilinx

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00