github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-24 19:42:18 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/techlibs/xilinx
History
Eddie Hung 60af2ca94d Transpose CARRY4 delays
2019-05-24 14:09:15 -07:00
..
tests
Improved xilinx "bram1" test
2015-04-09 17:12:12 +02:00
.gitignore
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
abc.box
Transpose CARRY4 delays
2019-05-24 14:09:15 -07:00
abc.lut
Modify LUT area cost to be same as old abc
2019-05-21 14:31:19 -07:00
arith_map.v
Instead of MUXCY/XORCY use CARRY4 (with timing)
2019-05-21 16:19:45 -07:00
brams_bb.v
Added Xilinx bram black-box modules
2015-04-06 08:44:30 +02:00
brams_init.py
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
brams_map.v
Revert BRAM WRITE_MODE changes.
2019-03-04 09:22:22 -08:00
brams.txt
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
cells_map.v
Fix/workaround symptom unveiled by #1023
2019-05-21 18:50:02 -07:00
cells_sim.v
Add whitebox support to DRAM
2019-05-23 08:58:57 -07:00
cells_xtra.sh
Add whitebox support to DRAM
2019-05-23 08:58:57 -07:00
cells_xtra.v
Add whitebox support to DRAM
2019-05-23 08:58:57 -07:00
drams_map.v
Xilinx DRAMS: RAM64X1D, RAM128X1D
2015-04-09 13:37:07 +02:00
drams.txt
Add "min bits" and "min wports" to xilinx dram rules
2019-05-23 11:32:28 -07:00
ff_map.v
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-04-28 12:36:04 -07:00
lut_map.v
Changes required for VPR place and route synth_xilinx.
2019-03-01 12:02:27 -08:00
Makefile.inc
Cleanup, call pmux2shiftx even without -nosrl
2019-04-22 12:14:37 -07:00
synth_xilinx.cc
Add whitebox support to DRAM
2019-05-23 08:58:57 -07:00