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YosysHQ.yosys
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techlibs
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common
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Clifford Wolf
362f4f996d
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-11 15:07:29 +01:00
..
.gitignore
…
adff2dff.v
…
cellhelp.py
…
cells.lib
…
cmp2lut.v
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
2019-11-11 15:07:29 +01:00
dff2ff.v
…
dummy.box
Use a dummy box file if none specified
2019-08-28 20:58:55 -07:00
gate2lut.v
…
Makefile.inc
Makefile: don't assume python is called
python3
2019-10-19 14:04:52 +08:00
mul2dsp.v
Missing (* mul2dsp *) for sliceB
2019-09-27 14:21:47 -07:00
pmux2mux.v
…
prep.cc
…
simcells.v
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
2019-08-06 04:47:55 +02:00
simlib.v
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"
2019-08-09 12:33:39 -07:00
synth.cc
Missing newline
2019-08-20 20:37:52 -07:00
techmap.v
…