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6b5507139ecc8b0d5e71bf81ae077ff3f5258210
YosysHQ.yosys
/
techlibs
/
common
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Scott Ashcroft
04bbd4e7e2
Make all vector-size related integer params in $print sim model signed
...
This fixes iverilog crashes on 32-bit, similar to
95944eb
for $mem.
2025-03-25 13:08:49 +00:00
..
choices
Merge pull request
#4789
from YosysHQ/emil/sklansky-adder
2024-12-03 11:33:13 +01:00
.gitignore
…
abc9_map.v
…
abc9_model.v
…
abc9_unmap.v
…
adff2dff.v
…
cellhelp.py
cellhelp.py: Cells can have tags
2024-10-15 07:35:41 +13:00
cells.lib
…
cmp2lcu.v
…
cmp2lut.v
…
cmp2softlogic.v
…
dff2ff.v
…
gate2lut.v
…
gen_fine_ffs.py
…
Makefile.inc
techmap: add a Sklansky option for
$lcu
mapping
2024-12-02 11:34:58 +01:00
mul2dsp.v
…
pmux2mux.v
…
prep.cc
…
simcells.v
Docs: Assert cell has group
2024-10-15 07:35:40 +13:00
simlib.v
Make all vector-size related integer params in $print sim model signed
2025-03-25 13:08:49 +00:00
smtmap.v
…
synth.cc
…
techmap.v
Merge pull request
#4818
from povik/macc_v2
2025-03-12 22:55:40 +01:00