This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-05-11 18:02:39 +00:00
Code
Issues
Releases
Wiki
Activity
Files
6bb72212d67ff6edd38eaf569bfdeb38eb83f3ec
YosysHQ.yosys
/
techlibs
/
intel
History
Emil J. Tywoniak
a000a7830c
intel: register bram celltypes
2026-05-05 21:35:14 +02:00
..
common
Fixed data/address width parameters
2024-03-06 02:45:07 +01:00
cyclone10lp
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneiv
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneive
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
max10
Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
Makefile.inc
synth_intel: Remove incomplete Arria 10 GX support.
2020-08-21 01:46:06 +02:00
synth_intel.cc
intel: register bram celltypes
2026-05-05 21:35:14 +02:00
