github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-28 04:59:20 +00:00
Code Issues Releases Wiki Activity
Files
6cd135a5eb918d30aeaf295e3e9fab9bf73134fb
YosysHQ.yosys/techlibs/intel_alm/common
History
Dan Ravensloft a2fb84fd0c intel_alm: direct M10K instantiation 
This reverts commit a3a90f6377.
2020-07-27 15:39:06 +02:00
..
abc9_map.v
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
2020-07-04 19:45:10 +02:00
abc9_model.v
intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
2020-07-04 19:45:10 +02:00
abc9_unmap.v
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
2020-07-04 19:45:10 +02:00
alm_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
alm_sim.v
intel_alm: add additional ABC9 timings
2020-07-23 11:57:07 +01:00
arith_alm_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
bram_m10k.txt
intel_alm: direct M10K instantiation
2020-07-27 15:39:06 +02:00
bram_m20k_map.v
synth_intel_alm: alternative synthesis for Intel FPGAs
2020-04-15 11:40:41 +02:00
bram_m20k.txt
synth_intel_alm: alternative synthesis for Intel FPGAs
2020-04-15 11:40:41 +02:00
dff_map.v
synth_intel_alm: Use dfflegalize.
2020-07-04 22:56:16 +02:00
dff_sim.v
intel_alm: add additional ABC9 timings
2020-07-23 11:57:07 +01:00
dsp_map.v
intel_alm: DSP inference
2020-07-05 05:39:20 +02:00
dsp_sim.v
intel_alm: add additional ABC9 timings
2020-07-23 11:57:07 +01:00
lutram_mlab.txt
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
megafunction_bb.v
intel_alm: direct M10K instantiation
2020-07-27 15:39:06 +02:00
mem_sim.v
intel_alm: direct M10K instantiation
2020-07-27 15:39:06 +02:00
quartus_rename.v
intel_alm: direct M10K instantiation
2020-07-27 15:39:06 +02:00