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YosysHQ.yosys/passes
Martin Schmölzer 4f6cda502d Add support for "fsm_export" synthesis attributes to fsm_export pass.
This allows to specify the file name for exported files directly in the HDL
source via the fsm_export=... attribute on the FSM state register.

Verilog example:
    (* fsm_export="my_fsm.kiss2" *)
    reg [3:0] state;

The fsm_export pass now also accepts the option "-noauto". This causes only
FSMs with the fsm_export attribute to be exported, any other FSMs are ignored.

Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
2013-01-08 09:43:35 +01:00
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