Clifford Wolf 6d69d4aaa8 Added support for constant bit- or part-select for memory writes

2014-07-17 13:13:21 +02:00

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asicworld

Added note to "make test": use git checkout of iverilog

2014-07-16 10:03:07 +02:00

hana

Added note to "make test": use git checkout of iverilog

2014-07-16 10:03:07 +02:00

realmath

Added note to "make test": use git checkout of iverilog

2014-07-16 10:03:07 +02:00

sat

now ignore init attributes on non-register wires in sat command

2014-07-05 11:18:38 +02:00

simple

Added support for constant bit- or part-select for memory writes

2014-07-17 13:13:21 +02:00

techmap

Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface

2014-07-16 14:08:51 +02:00

tools

Added note to "make test": use git checkout of iverilog

2014-07-16 10:03:07 +02:00