Ruben Undheim 545bcb37e8 Allow defining input ports as "input logic" in SystemVerilog

2016-06-20 20:16:37 +02:00

..

.gitignore

Updated .gitignore file for ilang and verilog frontends

2014-10-15 01:14:38 +02:00

const2ast.cc

Fixed segfault on invalid verilog constant 1'b_

2015-09-22 08:13:09 +02:00

Makefile.inc

Adjust makefiles to work with out-of-tree builds

2015-08-12 15:04:44 +02:00

preproc.cc

SystemVerilog also has assume(), added implicit -D FORMAL

2015-10-13 14:21:20 +02:00

verilog_frontend.cc

Small improvements in Verilog front-end docs

2016-05-20 16:21:35 +02:00

verilog_frontend.h

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

verilog_lexer.l

Added support for SystemVerilog packages with localparam definitions

2016-06-18 10:53:55 +02:00

verilog_parser.y

Allow defining input ports as "input logic" in SystemVerilog

2016-06-20 20:16:37 +02:00