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YosysHQ.yosys/techlibs/xilinx
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Marcelina Kościelnicka 871fc34ad4 xilinx: Add FDDRCPE and FDDRRSE blackbox cells. 
These are necessary primitives for proper DDR support on Virtex 2 and
Spartan 3.
2020-12-17 03:25:07 +01:00
..
tests
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
.gitignore
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
abc9_model.v
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
2020-05-14 10:33:56 -07:00
arith_map.v
Remove EXPLICIT_CARRY logic.
2020-07-23 00:56:09 +02:00
brams_init.py
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
cells_map.v
xilinx: Use dfflegalize.
2020-07-09 18:54:23 +02:00
cells_sim.v
Move signal declarations to before first use
2020-10-19 16:09:18 -06:00
cells_xtra.py
xilinx: Add FDDRCPE and FDDRRSE blackbox cells.
2020-12-17 03:25:07 +01:00
cells_xtra.v
xilinx: Add FDDRCPE and FDDRRSE blackbox cells.
2020-12-17 03:25:07 +01:00
ff_map.v
xilinx: Use dfflegalize.
2020-07-09 18:54:23 +02:00
lut4_lutrams.txt
xilinx: Add support for LUT RAM on LUT4-based devices.
2020-02-07 09:03:22 +01:00
lut6_lutrams.txt
xilinx: Add support for LUT RAM on LUT4-based devices.
2020-02-07 09:03:22 +01:00
lut_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
lutrams_map.v
Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
2019-12-16 12:06:47 -08:00
Makefile.inc
xilinx: Use dfflegalize.
2020-07-09 18:54:23 +02:00
mux_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
synth_xilinx.cc
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
xc2v_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc2v_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc3s_mult_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc3sa_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc3sda_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc3sda_dsp_map.v
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
xc4v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc5v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc6s_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc6s_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc6s_dsp_map.v
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
xc7_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc7_dsp_map.v
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
2020-09-23 09:15:24 -07:00
xc7_xcu_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xcu_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xcu_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xcup_urams_map.v
xilinx: Add URAM288 mapping for xcup
2019-10-23 11:47:44 +01:00
xcup_urams.txt
xilinx: Add URAM288 mapping for xcup
2019-10-23 11:47:44 +01:00
xilinx_dffopt.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00