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YosysHQ.yosys/backends
Martin Povišer 82fca50309 write_verilog: Handle edge case with non-pruned processes
This change only matters for processes that weren't processed by
`proc_rmdead` for which follow-up cases after a default case are treated
differently in Verilog and RTLIL semantics.
2024-01-06 17:05:02 +01:00
..
2023-08-12 11:59:39 +10:00
2024-01-05 20:41:16 +00:00
2023-06-20 10:42:05 +02:00
2023-08-12 11:59:39 +10:00
2021-06-09 12:42:52 +02:00
2023-08-12 11:59:39 +10:00
2023-08-12 11:59:39 +10:00