This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-02-12 19:27:12 +00:00
Code
Issues
Releases
Wiki
Activity
Files
713484fa66da705d2a274cdea590bd4634f48d5d
YosysHQ.yosys
/
techlibs
/
gowin
History
Pepijn de Vos
a3b25b4af8
Use -match-init to not synth contradicting init values
2019-12-03 15:12:25 +01:00
..
.gitignore
gowin: Add missing .gitignore entries
2019-11-22 14:40:36 +01:00
arith_map.v
use ADDSUB ALU mode to remove inverters
2019-10-21 12:00:27 +02:00
bram.txt
add 32-bit BRAM and byte-enables
2019-10-28 10:33:27 +01:00
brams_init3.vh
…
brams_init.py
…
brams_map.v
add 32-bit BRAM and byte-enables
2019-10-28 10:33:27 +01:00
cells_map.v
attempt to fix formatting
2019-11-25 14:50:34 +01:00
cells_sim.v
add IOBUF
2019-10-28 15:33:05 +01:00
determine_init.cc
…
dram.txt
…
drams_map.v
…
Makefile.inc
…
synth_gowin.cc
Use -match-init to not synth contradicting init values
2019-12-03 15:12:25 +01:00
