Miodrag Milanovic e6f7cf3b29 Update tests

2023-06-09 14:41:45 +02:00

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.gitignore

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abc9_dff.ys

Fix tests for check in equiv_opt

2022-10-07 16:04:51 +02:00

add_sub.ys

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adffs.ys

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asym_ram_sdp_read_wider.v

Asymmetric port ram tests with Xilinx

2023-02-21 05:23:14 +13:00

asym_ram_sdp_write_wider.v

Asymmetric port ram tests with Xilinx

2023-02-21 05:23:14 +13:00

asym_ram_sdp.ys

Asymmetric port ram tests with Xilinx

2023-02-21 05:23:14 +13:00

attributes_test.ys

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

blockram.ys

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

bug1460.ys

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bug1462.ys

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bug1480.ys

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bug1598.ys

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bug1605.ys

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bug3670.v

ABC9: Cell Port Bug Patch (#3670)

2023-04-22 16:24:36 -07:00

bug3670.ys

ABC9: Cell Port Bug Patch (#3670)

2023-04-22 16:24:36 -07:00

counter.ys

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dffs.ys

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dsp_abc9.ys

Add ABC9 DSP cascade test

2023-05-25 18:42:08 +01:00

dsp_cascade.ys

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dsp_fastfir.ys

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dsp_simd.ys

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fsm.ys

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latches.ys

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logic.ys

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lutram.ys

xilinx: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

macc_tb.v

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macc.sh

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macc.v

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macc.ys

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mul_unsigned.v

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mul_unsigned.ys

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mul.ys

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mux_lut4.ys

Update tests

2023-06-09 14:41:45 +02:00

mux.ys

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nosrl.ys

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opt_lut_ins.ys

Fix tests for check in equiv_opt

2022-10-07 16:04:51 +02:00

pmgen_xilinx_srl.ys

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priority_memory.v

Tests for ram_style = "huge"

2023-02-21 05:23:15 +13:00

priority_memory.ys

Tests for ram_style = "huge"

2023-02-21 05:23:15 +13:00

run-test.sh

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shifter.ys

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tribuf.sh

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tribuf.ys

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xilinx_dffopt_blacklist.txt

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xilinx_dffopt.ys

Fix tests for check in equiv_opt

2022-10-07 16:04:51 +02:00

xilinx_dsp.ys

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xilinx_srl.v

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xilinx_srl.ys

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