Jannis Harder 7203ba7bc1 Add bitwise $bweqx and $bwmux cells ...

The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.

2022-11-30 18:24:35 +01:00

..

cmds

Rst docs conversion (#3496)

2022-11-15 12:55:22 +01:00

equiv

Add "check -assert" to equiv_opt

2022-10-07 16:04:51 +02:00

fsm

mention prerequisites in fsm_detect and fsm help

2022-11-21 16:07:23 +01:00

hierarchy

Support importing verilog configurations using Verific

2022-11-25 13:02:11 +01:00

memory

Fitting help messages to 80 character width

2022-08-24 10:40:57 +12:00

opt

opt_expr: Fix shift/shiftx optimizations

2022-11-30 18:24:25 +01:00

pmgen

Fitting help messages to 80 character width

2022-08-24 10:40:57 +12:00

proc

proc_rom: Add special handling of const-0 address bits.

2022-05-18 17:32:30 +02:00

sat

sat: Add -set-def-formal option to force defined $any* outputs

2022-11-28 14:50:52 +01:00

techmap

Add bitwise $bweqx and $bwmux cells

2022-11-30 18:24:35 +01:00

tests

Add $bmux and $demux cells.

2022-01-28 23:34:41 +01:00