Claire Xenia Wolf d6e4d3f1ba Fix the tests we just broke ...

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>

2021-12-10 00:22:37 +01:00

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.gitignore

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abc9_dff.ys

ast: Use better parameter serialization for paramod names.

2021-03-18 00:52:00 +01:00

add_sub.ys

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adffs.ys

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attributes_test.ys

xilinx: Fix attributes_test.ys

2020-10-24 23:52:37 +02:00

blockram.ys

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bug1460.ys

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bug1462.ys

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bug1480.ys

Cleanup tests

2020-02-27 10:17:29 -08:00

bug1598.ys

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bug1605.ys

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counter.ys

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dffs.ys

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dsp_abc9.ys

xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)

2020-09-23 09:15:24 -07:00

dsp_cascade.ys

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dsp_fastfir.ys

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dsp_simd.ys

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fsm.ys

FfData: some refactoring.

2021-10-07 04:24:06 +02:00

latches.ys

opt_expr: Remove -clkinv option, make it the default.

2020-07-31 00:08:15 +02:00

logic.ys

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lutram.ys

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macc_tb.v

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macc.sh

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macc.v

tests: xilinx macc test to have initval, shorten BMC depth for runtime

2020-05-25 10:09:05 -07:00

macc.ys

tests: xilinx macc test to have initval, shorten BMC depth for runtime

2020-05-25 10:09:05 -07:00

mul_unsigned.v

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mul_unsigned.ys

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mul.ys

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mux_lut4.ys

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mux.ys

xilinx_dffopt: Don't crash on missing IS_*_INVERTED.

2021-01-27 00:32:00 +01:00

nosrl.ys

xilinx: Fix srl regression.

2020-07-12 23:41:27 +02:00

opt_lut_ins.ys

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pmgen_xilinx_srl.ys

satgen: Add support for dffe, sdff, sdffe, sdffce cells.

2020-07-24 03:19:21 +02:00

run-test.sh

tests: Centralize test collection and Makefile generation

2020-09-21 15:07:02 +02:00

shifter.ys

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tribuf.sh

Fix the tests we just broke

2021-12-10 00:22:37 +01:00

tribuf.ys

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xilinx_dffopt_blacklist.txt

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xilinx_dffopt.ys

xilinx_dffopt: Don't crash on missing IS_*_INVERTED.

2021-01-27 00:32:00 +01:00

xilinx_dsp.ys

tests: read +/xilinx/cell_sim.v before xilinx_dsp test

2020-04-22 17:50:30 -07:00

xilinx_srl.v

tests: fix some test warnings

2020-05-25 10:07:58 -07:00

xilinx_srl.ys

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