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YosysHQ.yosys/frontends/ast
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Zachary Snow 4b2f977331 genrtlil: fix signed port connection codegen failures 
This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.
2021-02-05 19:51:30 -05:00
..
ast.cc
ast: fix dump_vlog display of casex/casez
2021-01-29 16:28:15 +01:00
ast.h
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
dpicall.cc
dpi: Support for chandle type
2021-01-23 22:24:31 +00:00
genrtlil.cc
genrtlil: fix signed port connection codegen failures
2021-02-05 19:51:30 -05:00
Makefile.inc
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
simplify.cc
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00