dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
10 lines
218 B
Verilog
10 lines
218 B
Verilog
module test(input CLK, ADDR,
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input [7:0] DIN,
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output reg [7:0] DOUT);
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reg [7:0] mem [0:1];
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always @(posedge CLK) begin
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mem[ADDR] <= DIN;
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DOUT <= mem[ADDR];
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end
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endmodule
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