Clifford Wolf bdc316db50 Added $anyseq cell type

2016-10-14 15:24:03 +02:00

..

blif

Added $ff and $_FF_ cell types

2016-10-12 01:18:39 +02:00

btor

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

edif

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

ilang

Added $global_clock verilog syntax support for creating $ff cells

2016-10-14 12:33:56 +02:00

intersynth

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

json

write_json: also write module attributes.

2016-07-12 06:32:04 +00:00

smt2

Added $anyseq cell type

2016-10-14 15:24:03 +02:00

smv

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

spice

Also escape "=" in spice output

2016-05-20 16:43:13 +02:00

verilog

Bugfix in partial mem write handling in verilog back-end

2016-08-20 13:06:06 +02:00