github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-03-27 18:50:03 +00:00
Code Issues Releases Wiki Activity
Files
76efbcc15f06b1b6decbbab1036d52abe9fb64e8
YosysHQ.yosys/techlibs/altera_intel
History
Larry Doolittle 2021ddecb3 Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
..
cycloneiv
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
max10
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
lpm_functions.v
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
Makefile.inc
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
2017-04-05 23:01:29 -05:00
synth_intel.cc
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00