Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_

2014-07-27 11:18:30 +02:00

..

APPNOTE_011_Design_Investigation

Improved "make manual" and "make clean"

2014-02-11 12:55:58 +01:00

CHAPTER_Eval

Renamed manual/FILES_* directories

2014-01-28 06:55:47 +01:00

CHAPTER_Prog

Refactoring: Renamed RTLIL::Design::modules to modules_

2014-07-27 11:18:30 +02:00

CHAPTER_StateOfTheArt

Renamed manual/FILES_* directories

2014-01-28 06:55:47 +01:00

PRESENTATION_ExAdv

Progress in presentation

2014-02-21 14:59:59 +01:00

PRESENTATION_ExOth

Progress in presentation

2014-06-21 16:33:33 +02:00

PRESENTATION_ExSyn

Progress in presentation

2014-06-21 16:33:33 +02:00

PRESENTATION_Intro

Progress in presentation

2014-06-26 22:05:39 +02:00

PRESENTATION_Prog

Refactoring: Renamed RTLIL::Design::modules to modules_

2014-07-27 11:18:30 +02:00

.gitignore

presentation progress

2014-01-29 12:15:38 +01:00

APPNOTE_010_Verilog_to_BLIF.tex

Fixed bug in example prog in appnote 011

2013-12-05 18:15:14 +01:00

APPNOTE_011_Design_Investigation.tex

Finished AppNote 011

2013-12-08 15:12:32 +01:00

appnotes.sh

Improved "make manual" and "make clean"

2014-02-11 12:55:58 +01:00

CHAPTER_Appnotes.tex

Added Yosys Manual

2013-07-20 15:19:12 +02:00

CHAPTER_Approach.tex

Typos and grammar fixes through chapter 4.

2014-05-02 03:08:40 -06:00

CHAPTER_Auxlibs.tex

Added Yosys Manual

2013-07-20 15:19:12 +02:00

CHAPTER_Auxprogs.tex

Added Yosys Manual

2013-07-20 15:19:12 +02:00

CHAPTER_Basics.tex

Typos and grammar fixes through chapter 2.

2014-04-11 02:42:59 -06:00

CHAPTER_CellLib.tex

Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal

2014-07-16 11:38:02 +02:00

CHAPTER_Eval.tex

Added Yosys Manual

2013-07-20 15:19:12 +02:00

CHAPTER_Intro.tex

Typos and grammar fixes through chapter 2.

2014-04-11 02:42:59 -06:00

CHAPTER_Optimize.tex

Added Yosys Manual

2013-07-20 15:19:12 +02:00

CHAPTER_Overview.tex

Typos and grammar fixes through chapter 4.

2014-05-02 03:08:40 -06:00

CHAPTER_Prog.tex

Renamed manual/FILES_* directories

2014-01-28 06:55:47 +01:00

CHAPTER_StateOfTheArt.tex

Renamed manual/FILES_* directories

2014-01-28 06:55:47 +01:00

CHAPTER_Techmap.tex

Moved common techlib files to techlibs/common

2013-09-15 11:52:57 +02:00

CHAPTER_Verilog.tex

Added RTLIL and Liberty syntax highlighting to manual

2013-07-25 14:00:16 +02:00

clean.sh

POSIX find requires a path argument.

2014-04-04 16:51:27 -06:00

command-reference-manual.tex

Updated manual/command-reference-manual.tex

2013-12-28 12:14:47 +01:00

literature.bib

Added Yosys Manual

2013-07-20 15:19:12 +02:00

manual.sh

Added first presentation slides

2014-01-27 17:08:19 +01:00

manual.tex

Typos and grammar fixes through chapter 2.

2014-04-11 02:42:59 -06:00

PRESENTATION_ExAdv.tex

Progress in presentation

2014-06-26 22:05:39 +02:00

PRESENTATION_ExOth.tex

Progress in presentation

2014-06-26 22:05:39 +02:00

PRESENTATION_ExSyn.tex

Progress in presentation

2014-06-26 22:05:39 +02:00

PRESENTATION_Intro.tex

Progress in presentation

2014-06-29 09:14:49 +02:00

PRESENTATION_Prog.tex

Progress in presentation

2014-06-26 22:05:39 +02:00

presentation.sh

Progress in presentation

2014-06-22 12:50:29 +02:00

presentation.tex

small changes in presentation

2014-07-02 06:16:31 +02:00

weblinks.bib

Added Yosys Manual

2013-07-20 15:19:12 +02:00