Clifford Wolf 77e5968323 Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API

2014-03-14 11:45:44 +01:00

..

bitpattern.h

initial import

2013-01-05 11:13:26 +01:00

calc.cc

Strictly zero-extend unsigned A-inputs of shift operations

2014-03-06 11:53:37 +01:00

celltypes.h

Fixed const folding of $bu0 cells

2014-02-27 04:09:32 +01:00

compatibility.cc

Merged OSX fixes from Siesh1oo with some modifications

2014-03-13 12:48:10 +01:00

compatibility.h

Hotfix for kernel/compatibility.h

2014-03-13 12:55:15 +01:00

consteval.h

Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux

2014-01-03 17:30:50 +01:00

driver.cc

- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().

2014-03-12 23:17:14 +01:00

log.cc

Merged OSX fixes from Siesh1oo with some modifications

2014-03-13 12:48:10 +01:00

log.h

Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys

2014-03-11 14:24:24 +01:00

register.cc

Merged OSX fixes from Siesh1oo with some modifications

2014-03-13 12:48:10 +01:00

register.h

- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().

2014-03-12 23:17:14 +01:00

rtlil.cc

Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API

2014-03-14 11:45:44 +01:00

rtlil.h

Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API

2014-03-14 11:45:44 +01:00

satgen.h

Added libs/minisat (copy of minisat git master)

2014-03-12 10:17:51 +01:00

sigtools.h

Some fixes to improve determinism

2013-08-09 12:42:32 +02:00