Clifford Wolf 7a67add95d Fixed parsing of empty positional cell ports

2016-07-25 12:48:03 +02:00

..

.gitignore

Updated .gitignore file for ilang and verilog frontends

2014-10-15 01:14:38 +02:00

const2ast.cc

Fixed segfault on invalid verilog constant 1'b_

2015-09-22 08:13:09 +02:00

Makefile.inc

Adjust makefiles to work with out-of-tree builds

2015-08-12 15:04:44 +02:00

preproc.cc

SystemVerilog also has assume(), added implicit -D FORMAL

2015-10-13 14:21:20 +02:00

verilog_frontend.cc

No tristate warning message for "read_verilog -lib"

2016-07-23 11:56:53 +02:00

verilog_frontend.h

No tristate warning message for "read_verilog -lib"

2016-07-23 11:56:53 +02:00

verilog_lexer.l

After reading the SV spec, using non-standard predict() instead of expect()

2016-07-21 13:34:33 +02:00

verilog_parser.y

Fixed parsing of empty positional cell ports

2016-07-25 12:48:03 +02:00