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YosysHQ.yosys/kernel
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Eddie Hung 7ad7f41bc5 kernel: share a single CellTypes within a pass
2020-03-18 12:21:40 -07:00
..
bitpattern.h
…
calc.cc
…
cellaigs.cc
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
cellaigs.h
…
celledges.cc
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
celledges.h
…
celltypes.h
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
consteval.h
Revert "SigSet<Cell*> to use stable compare class"
2019-09-13 09:49:15 -07:00
cost.h
Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)
2019-08-11 11:39:46 +02:00
driver.cc
Handle expect no warnings together with expected
2020-02-22 10:52:46 +01:00
hashlib.h
…
log.cc
Fix compilation for emcc
2020-03-11 22:09:24 +08:00
log.h
Handle expect no warnings together with expected
2020-02-22 10:52:46 +01:00
macc.h
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
modtools.h
kernel: share a single CellTypes within a pass
2020-03-18 12:21:40 -07:00
register.cc
Add ScriptPass::run_nocheck and use for abc9
2020-03-09 14:34:22 +00:00
register.h
Add ScriptPass::run_nocheck and use for abc9
2020-03-09 14:34:22 +00:00
rtlil.cc
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
rtlil.h
Add and use SigSpec::reverse()
2020-01-28 10:37:16 -08:00
satgen.h
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
sigtools.h
Spacing
2019-09-13 16:30:44 -07:00
timinginfo.h
Small fixes
2020-02-27 10:29:53 -08:00
utils.h
…
yosys.cc
Fix compilation for emcc
2020-03-11 22:09:24 +08:00
yosys.h
log_dump() to support State enum
2019-10-02 17:49:07 -07:00