github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-29 05:21:15 +00:00
Code Issues Releases Wiki Activity
Files
7bb0a1913e46cc205e89e1fda88eb31c85da4d86
YosysHQ.yosys/tests/svinterfaces
History
Krystine Sherwin 7bb0a1913e hierarchy.cc: Raise error on positional interface 
Add test to check that it does error.
2025-10-15 09:10:33 +13:00
..
.gitignore
Add missing .gitignore
2018-12-06 07:29:37 +01:00
load_and_derive.sv
Add a test for interfaces on modules loaded on-demand
2021-07-14 22:54:50 -04:00
load_and_derive.ys
Add a test for interfaces on modules loaded on-demand
2021-07-14 22:54:50 -04:00
ondemand.sv
Add a test for interfaces on modules loaded on-demand
2021-07-14 22:54:50 -04:00
positional_args.ys
hierarchy.cc: Raise error on positional interface
2025-10-15 09:10:33 +13:00
resolve_types.sv
Resolve package types in interfaces (#3658)
2023-02-12 18:25:39 -05:00
resolve_types.ys
Resolve package types in interfaces (#3658)
2023-02-12 18:25:39 -05:00
run_simple.sh
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00
run-test.sh
hierarchy.cc: Raise error on positional interface
2025-10-15 09:10:33 +13:00
runone.sh
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00
svinterface1_ref.v
Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 22:40:53 +02:00
svinterface1_tb.v
Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 22:40:53 +02:00
svinterface1.sv
Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 22:40:53 +02:00
svinterface_at_top_ref.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top_tb_wrapper.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top_tb.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top_wrapper.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top.sv
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00