Scott Ashcroft 04bbd4e7e2 Make all vector-size related integer params in $print sim model signed ...

This fixes iverilog crashes on 32-bit, similar to 95944eb for $mem.

2025-03-25 13:08:49 +00:00

..

choices

Merge pull request #4789 from YosysHQ/emil/sklansky-adder

2024-12-03 11:33:13 +01:00

.gitignore

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abc9_map.v

techmap: Add support for [] wildcards in techmap_celltype.

2020-08-02 22:46:48 +02:00

abc9_model.v

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

abc9_unmap.v

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

adff2dff.v

Fix syntax error in adff2dff.v

2021-02-24 01:07:34 +01:00

cellhelp.py

cellhelp.py: Cells can have tags

2024-10-15 07:35:41 +13:00

cells.lib

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cmp2lcu.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

cmp2lut.v

verilog: significant block scoping improvements

2021-01-31 09:42:09 -05:00

cmp2softlogic.v

techlibs: Add cmp2softlogic.v to common

2023-11-13 10:42:12 +01:00

dff2ff.v

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gate2lut.v

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gen_fine_ffs.py

simcells: Apply group tags

2024-10-15 07:35:40 +13:00

Makefile.inc

techmap: add a Sklansky option for $lcu mapping

2024-12-02 11:34:58 +01:00

mul2dsp.v

Fix files with CRLF line endings

2021-06-09 12:16:33 +02:00

pmux2mux.v

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prep.cc

Run future as part of prep

2023-09-13 11:32:36 +02:00

simcells.v

Docs: Assert cell has group

2024-10-15 07:35:40 +13:00

simlib.v

Make all vector-size related integer params in $print sim model signed

2025-03-25 13:08:49 +00:00

smtmap.v

Add smtmap.v describing the smt2 backend's behavior for undef bits

2022-10-20 15:48:18 +02:00

synth.cc

synth: Fix out-of-sync help message

2024-03-06 14:55:43 +01:00

techmap.v

Merge pull request #4818 from povik/macc_v2

2025-03-12 22:55:40 +01:00