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7bd2144d03ae5daffbcddea609d2db7df7b751a2
YosysHQ.yosys
/
frontends
/
verilog
History
Clifford Wolf
36ea98385f
Add warning for SV "restrict" without "property"
...
Signed-off-by: Clifford Wolf <
clifford@clifford.at
>
2018-11-04 15:57:17 +01:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Convert more log_error() to log_file_error() where possible.
2018-07-20 09:37:44 -07:00
Makefile.inc
Add "make coverage"
2018-08-27 14:22:21 +02:00
preproc.cc
Support SystemVerilog `` extension for macros
2018-05-17 00:09:56 -04:00
verilog_frontend.cc
Add "read_verilog -noassert -noassume -assert-assumes"
2018-09-24 20:51:16 +02:00
verilog_frontend.h
Add "read_verilog -noassert -noassume -assert-assumes"
2018-09-24 20:51:16 +02:00
verilog_lexer.l
Merge pull request
#659
from rubund/sv_interfaces
2018-10-18 10:58:47 +02:00
verilog_parser.y
Add warning for SV "restrict" without "property"
2018-11-04 15:57:17 +01:00
