Krystine Sherwin 7c5b10fe50

cellref: Add json dump ...

New `help -dump-cells-json <file>` to dump cells list.
Add 'group' field to SimHelper class/struct with defaults to gate_other and word_other depending on source (simcells or simlib).
Add 'unary' group to unary operator cells for testing (based on internal cell library docs page).

2024-10-15 07:25:27 +13:00

..

achronix

techlibs: fix typo in help message

2023-11-13 16:29:52 +13:00

anlogic

Fix some synth_* help messages

2024-03-18 11:33:18 +13:00

common

cellref: Add json dump

2024-10-15 07:25:27 +13:00

coolrunner2

Blackbox all whiteboxes after synthesis

2021-03-17 21:07:20 +00:00

easic

Fixing old e-mail addresses and deadnames

2021-06-08 00:39:36 +02:00

ecp5

Fix some synth_* help messages

2024-03-18 11:33:18 +13:00

efinix

Merge pull request #4285 from YosysHQ/typo_fixup

2024-04-25 09:54:48 +12:00

fabulous

Fix some synth_* help messages

2024-03-18 11:33:18 +13:00

gatemate

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

gowin

Gowin. Add the EMCU primitive.

2024-09-11 10:18:51 +10:00

greenpak4

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

ice40

Fix some synth_* help messages

2024-03-18 11:33:18 +13:00

intel

Fitting help messages to 80 character width

2022-08-24 10:40:57 +12:00

intel_alm

intel_alm: drop quartus support

2024-05-03 11:32:33 +01:00

lattice

Fix some synth_* help messages

2024-03-18 11:33:18 +13:00

microchip

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

nanoxplore

Cleanup of synth_nanoxplore pass

2024-09-03 10:15:50 +02:00

nexus

Fix some synth_* help messages

2024-03-18 11:33:18 +13:00

quicklogic

rtlil: represent Const strings as std::string

2024-10-14 06:28:12 +02:00

sf2

Test fixes for latest iverilog

2022-09-21 15:46:43 +02:00

xilinx

Merge pull request #4649 from YosysHQ/emil/synth-xilinx-json

2024-10-14 06:45:14 -07:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00