Robert O'Callahan 09b493cfcd Update techlibs to avoid bits()

2025-09-16 03:17:23 +00:00

..

.gitignore

gatemate: Add LUT tree library script

2022-06-27 10:09:48 +01:00

arith_map.v

synth_gatemate: Initial implementation

2021-11-13 21:53:25 +01:00

brams_init_20.vh

synth_gatemate: Initial implementation

2021-11-13 21:53:25 +01:00

brams_init_40.vh

synth_gatemate: Revise block RAM read modes and initialization

2021-11-13 21:53:25 +01:00

brams_map.v

gatemate: Set unused BRAM inputs to 'bx

2025-04-28 14:42:16 +02:00

brams.txt

gatemate: WRITE_THROUGH mode change

2025-04-18 14:16:02 +02:00

cells_bb.v

gatemate: Add CC_SERDES parameters and update port names

2025-01-10 10:25:10 +01:00

cells_sim.v

Change to blocking assignments in non-clocked process.

2025-04-23 17:13:37 +02:00

gatemate_foldinv.cc

Update techlibs to avoid bits()

2025-09-16 03:17:23 +00:00

inv_map.v

gatemate: Add LUT tree library script

2022-06-27 10:09:48 +01:00

lut_map.v

synth_gatemate: Initial implementation

2021-11-13 21:53:25 +01:00

make_lut_tree_lib.py

gatemate: Add LUT tree library script

2022-06-27 10:09:48 +01:00

Makefile.inc

gatemate: Add LUT tree library script

2022-06-27 10:09:48 +01:00

mul_map.v

synth_gatemate: Rename multiplier factor parameters

2021-11-13 21:53:25 +01:00

mux_map.v

synth_gatemate: Initial implementation

2021-11-13 21:53:25 +01:00

reg_map.v

gatemate: Enable register initialization

2023-02-15 17:29:01 +01:00

synth_gatemate.cc

Remove .c_str() from stringf parameters

2025-09-01 23:34:42 +00:00