Emil J. Tywoniak 19a4c29a0e Revert "intel: register bram celltypes" ...

This reverts commit 16785a7f75.

2026-05-22 18:40:16 +02:00

..

achronix

Add check before flatten in synth_*.

2026-05-05 14:06:58 +02:00

analogdevices

Add check before flatten in synth_*.

2026-05-05 14:06:58 +02:00

anlogic

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

common

Convert RTLIL::unescape_id of IdString to unescape()

2026-05-16 19:49:45 +02:00

coolrunner2

Add check before flatten in synth_*.

2026-05-05 14:06:58 +02:00

easic

Add check before flatten in synth_*.

2026-05-05 14:06:58 +02:00

efinix

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

fabulous

Add check before flatten in synth_*.

2026-05-05 14:06:58 +02:00

gatemate

Merge pull request #5844 from YosysHQ/lofty/abc-refactor-5

2026-05-06 13:40:15 +00:00

gowin

gowin: replace positional arguments in cells_sim.v with named

2026-05-22 18:39:42 +02:00

greenpak4

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

ice40

pmgen: hold sigmap pointer instead of owning it

2026-05-22 18:40:01 +02:00

intel

Revert "intel: register bram celltypes"

2026-05-22 18:40:16 +02:00

intel_alm

Revert "intel: register bram celltypes"

2026-05-22 18:40:16 +02:00

lattice

Refactored uses of log_id()

2026-05-08 20:59:24 -07:00

microchip

pmgen: hold sigmap pointer instead of owning it

2026-05-22 18:40:01 +02:00

nanoxplore

Add check before flatten in synth_*.

2026-05-05 14:06:58 +02:00

quicklogic

pmgen: hold sigmap pointer instead of owning it

2026-05-22 18:40:01 +02:00

sf2

Add check before flatten in synth_*.

2026-05-05 14:06:58 +02:00

xilinx

xilinx_dsp: signorm compatibility

2026-05-22 18:40:01 +02:00

.gitignore

pmgen: Move passes out of pmgen folder

2025-01-31 15:18:28 +13:00

fix_mod.py

Add and use fix_mod.py

2026-01-28 07:45:58 +13:00