Clifford Wolf db98a18edb Enabled AST/Verilog front-end optimizations per default

2013-06-10 13:19:04 +02:00

..

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00

const2ast.cc

Added SAT generator and simple sat_solve command

2013-06-07 13:59:13 +02:00

lexer.l

Added support for verilog === operator

2013-05-07 14:35:40 +02:00

Makefile.inc

initial import

2013-01-05 11:13:26 +01:00

parser.y

Added SAT generator and simple sat_solve command

2013-06-07 13:59:13 +02:00

preproc.cc

added option '-Dname[=definition]' to command 'read_verilog'

2013-05-19 17:07:52 +02:00

verilog_frontend.cc

Enabled AST/Verilog front-end optimizations per default

2013-06-10 13:19:04 +02:00

verilog_frontend.h

added option '-Dname[=definition]' to command 'read_verilog'

2013-05-19 17:07:52 +02:00